FMCADDA-101

Dual Channel 12-bit A/D @ 1 GSPS

Dual Channel 16-bit D/A @ 1 GSPS

Description

The FMCADDA-101 is a dual channel ADC and dual channel DAC FMC. The FMCADDA-101 provides two channels of 12-bit A/D @ 1 GSPS and two channels of 16-bit D/A @ 1 GSPS enabling simultaneous sampling at a maximum rate of 1 GSPS.The sample clock can be supplied externally through a coax connection or supplied by an internal clock source (optionally locked to an external reference).Additionally a trigger input for customized sampling control is available.The FMCADDA-101 daughter card is mechanically and electrically compliant to FMC standard (ANSI/VITA 57.1). The card has a high-pin count (HPC) connector, front panel I/O, and can be used in a conduction cooled environment as well as a conventionally (air) cooled environment.The FMCADDA-101 allows flexible control on clock source, sampling frequency, and calibration through a serial communication bus. The FMCADDA-101 card is equipped with power supply and temperature monitoring with several power-down modes to switch off unused functions, reducing system level power and heat, well suited for software defined radio (SDR), battery or other low power source applications.This is ideal for applications such as airborne where power demand effects mission range and on-station mission time.

Features

    • Dual – A/D – D/A Channel Operation

       ‣ 2-Channels 12-bit 1.0 Gsps A/D

       ‣ 2-Channels 16-bit 1.0 Gsps D/A

    • VITA 57.1-2010 compliant

    • Conduction Cooled – Standard Option

    • Single ended AC-coupled analog input.

    • Clock Source, Sampling Frequency, and Calibration through an SPI communication bus

    • Flexible clock tree enables:

       ‣ internal clock

       ‣ external clock

    • Mil-I-46058c Conformal Coating Compliant (optional)

    • HPC – High Pin Count Connector

    • 6 front panel SSMC connectors

    • 2Kbit EEPROM (24LC02B) accessible from the Host via I2C bus

    • JTAG – CPLD device is included in the JTAG chain accessible from the FMC connection

    • 4 rocket I/O pairs and 4 LVTTL lines available on the front panel

    • HDMI connector for user defined signaling

(Click Block Diagram to Enlarge)

Application

  • Direct RF Down Conversion

  • Software defined radio (SDR)

  • RADAR/SONAR Electronic Warfare

  • Ultra Wideband Satellite Digital Receiver and Transmitter

  • Medical equipment

  • Aerospace and test measurement instruments

Performance

The FMCADDA-101's A/D channels are based on the TI ADS5400 which can operate in 1-bus or 2-bus mode. In 1-bus mode all data is transferred to output port A at a maximum rate of 1000Gbps per DDR LVDS pair. In 2-bus more the data is de-multiplexed over output port A and B at a maximum rate of 500Gpbs per DDR LVDS pair. Each of the D/A channels has an independent DDR LVDS data bus. The full rate of 1Gsps is supported, but the digital transfer rate can be lowered by enabling the interpolation (x2 or x4) in the D/A devices. Each of the two D/A channels have an independent DDR LVDS data bus. The full rate of 1Gsps is supported, optionally the digital transfer rate can be lowered by enabling the interpolation (x2 or x4) in the D/A devices.