ADC and DAC>

  • FMCADDA-102

    Quad Channel 16-bit A/D @ 1 GSPS

    Quad Channel 16-bit D/A @ 1.25 GSPS

    Simultaneous Sampling @ 1 GSPS

    Description

    The FMCADDA-102 provides four 16-bit A/D channels up to 1Gsps and four 16-bit D/A channels up to 1.25Gsps data rate and up to 2.8Gsps sample rate with interpolation. The devices can function up to 1Gsps during simultaneously D/A and A/D operation due to a shared clock source. The design is based on Texas Instruments' ADS54J60 Analog-to-Digital converter and Texas Instruments' DAC39J84 Digital-to-Analog converter. The sample clock can be supplied externally through a coax connection or supplied by an internal clock source (optionally locked to an external reference). Additionally, a trigger input is available for customized synchronization. The FMCADDA-102 is mechanically and electrically compliant to the FMC standard (ANSI/VITA 57.1). The card connects to an FPGA carrier card through a standard high-pin count (HPC) connector. Front panel I/O can optionally be populated with MMCX or SSMC coaxial connectors. Analog I/O is DC coupled. The FMCADDA-102 is designed to be used in convection or conduction cooled environments. When paired with the latest FPGA carrier cards such as the 4DSP PC821 with Xilinx Ultrascale technology, customers can innovate high performance algorithms on an industry standard platforms.

     

    Features

        • Quad - A/D - D/A Channel Operation

           ‣ Quad Channels 16-bit 1.00 GSPS A/D

           ‣ Quad Channels 16-bit 1.25 GSPS D/A

           ‣ Simultaneous sampling on all channels up to 1 GSPS

        • VITA 57.1-2010 compliant

        • Conduction Cooled – Standard Option

        • Single ended DC-coupled analog input.

        • Clock Source, Sampling Frequency, and Calibration through an SPI communication bus

        • Internal clock or external clock

        • Mil-I-46058c Conformal Coating Compliant (optional)

        • HPC – High Pin Count Connector

        • 10 front panel SSMC or MMCX connectors

        • 2Kbit EEPROM (24LC02B) accessible from the Host via I2C bus

        • JTAG – CPLD device is included in the JTAG chain accessible from the FMC connection

     

                                    (Click Block Diagram to Enlarge)

    Application

        • Software defined radio (SDR)

        • 4x4 MIMO

        • Digital Beam Forming

        • RADAR/SONAR Electronic Warfare

        • Experimental Physics

        • Analog record and playback systems

        • Aerospace and test measurement instruments